High Performance IVR with PKG-Level Inductor
Package-Level Inductor & PMIC Design for High Performance IVR
- Samsung Electronics TSP ( 2020.09~)
This study aims to develop a high-performance inductor structure using packaging technology and design a highly efficient IVR by simultaneously optimizing both package and circuit design to minimize energy loss and area. Recent trends in DC-DC converter technology show an increase in operating frequency along with a reduction in inductor size and area. With the advancement of 2.5D/3D packaging technology, it is now possible to implement various three-dimensional inductor structures at the package level, and the use of magnetic materials, which are difficult to integrate into chips, has also become feasible. Additionally, by optimizing the placement of inductors and capacitors considering system performance, the losses in the PDN can be reduced. In this study, we develop an inductor structure that provides stable inductance values at high frequencies while minimizing Eddy current and skin effect, leveraging the latest packaging technology.
SI/PI Solutions for Heterogeneous Integration
Bridge Die-based Heterogeneous Integration Packaging Solutions
- HANA Micron ( 2022.10~ )
Heterogeneous integration packaging solutions are technologies that integrate semiconductor chips with different functions into a single package, playing a key role in high-performance computing and high-density system implementation. This technology allows for the integration of various processors, memory, and specialized function chips into a single package, achieving both design flexibility and performance improvements. In particular, the bridge die optimizes signal transmission between chips, minimizing power consumption and latency, while saving package space to enable high performance even in compact devices. For these reasons, this solution is gaining attention in various fields such as next-generation mobile devices, data centers, and AI accelerators. This project aims to develop signal integrity (SI) and power integrity (PI) design solutions for a heterogeneous integration package with high-speed, high-bandwidth interconnects at 6.4 Gbps using a silicon bridge for HBM3 (High Bandwidth Memory 3).
Optimum Power Integrity Solutions for 2.5D/3D Package
System-Level Power Integrity Solutions for 2.5D/3D Package
In 2.5D and 3D packaging, Power Integrity (PI) solutions are crucial for managing increasingly complex power distribution networks due to high-density integration. As interconnections within the package and between chips become more intricate, it is important to optimize the resistance and impedance of power delivery paths to minimize signal interference. Ensuring power integrity at the system level, rather than just at the component level, is essential for maintaining uniform power distribution and improving efficiency in multi-die environments. By effectively managing power integrity, systems can maintain stable performance and high reliability. Maximizing power efficiency in environments with complex power demands and high integration density is a key challenge in next-generation packaging technologies.
Thermal and Power Integrity Co-optimization for 3D-IC
Reinforcement Learning-based Thermal and Power Integrity Co-optimization
As 3D IC technology becomes increasingly widespread, maintaining thermal management and power integrity simultaneously is becoming more challenging due to higher power density, complex interconnects, and limited cooling paths. In response, this research focuses on the simultaneous optimization of thermal and power integrity in 3D ICs using Reinforcement Learning (RL) techniques. RL intelligently explores the vast design space, enabling real-time adjustments and trade-offs between thermal management and power integrity. This allows for effective floorplanning, voltage regulation, and dynamic thermal control, ensuring stable performance and reliability. The RL-based algorithm optimizes both the power delivery network and thermal dissipation paths, preventing overheating and maintaining robust power distribution. Ultimately, the goal is to develop more efficient 3D IC designs by minimizing thermal and power delivery issues, thereby improving overall system performance.
