ML-based Semiconductor Modeling and Simulation: From TCAD to Circuit Simulation
ML-based Semiconductor Modeling and Simulation: From TCAD to Circuit Simulation
- Institute for Information & communication Technology Planning & evaluation (IITP) ( 2021.04 ~ )
As transistor materials, structures and integration methods have evolved to improve circuit integration according to Moore's Law, transistor sizes have been reduced to the nanometer scale. In next-generation devices such as gate all-around FET (GAAFET), the channel length is about 15 nm, approaching atomic size (about 1 nm), which increases the impact of quantum effects on the electrical characteristics of these devices. This has necessitated more accurate simulation approaches and modeling methodologies. However, the physics-driven technology computer-aided design (TCAD)-to-simulation program with integrated circuit emphasis (SPICE) flow method, which relies solely on physical knowledge, encountered bottlenecks due to high computational costs, reliability issues, and modeling challenges. We address these issues in the physics-driven TCAD-to-SPICE flow with novel machine learning techniques.
Emerging device simulation & analysis
We are researching various emerging devices using Sentaurus TCAD simulations to improve the reliability and performance such as gate-all-around FET (GAAFET), complementary FET (CFET), ferroelectric FET (FeFET), and DRAM (BCAT, VCT).
Device modeling
Device modeling is essential for circuit simulations and designs, we are researching various device modeling methodologies such as physics-based compact model, NN-assisted physics-based compact model parameter extractor, and NN-based compact model.
Sampling methodology
In the field of scientific machine learning, it is difficult to obtain sufficient data because training data must be extracted from high-fidelity simulators. Therefore, we are researching efficient sampling methodologies such as model uncertainty reduction-based training sample minimization, expected improvement-based sub-3nm device optimization, and failure region sampling & circuit surrogate model-based yield estimation method.
Scientific machine learning
We are also researching various ways to improve generalization performance based on the an understanding of both physics and machine learning methods. Our research covers diverse areas such as multi-fidelity modeling, grey box modeling, hybrid modeling, physics-informed neural networks, neural operators, and neural network-assisted physics models.
Parasitic R&C extraction
In addition, as the scale-down of node technology intensifies, the influence of parasitic RC components in interconnects has increased. Accurate parasitic extraction (PEX) is critical in modern high-performance integrated circuit (IC) design. Parasitic primarily refers to the resistance and capacitance present in an IC's interconnects, which have a significant impact on signal delay and circuit performance. PEX involves modeling the electromagnetic effects between interconnects and calculating the values of these R/C components. In particular, capacitance extraction is a critical issue due to the complexity of the calculation and the integration between many on-ship interconnect segments. The accuracy of PEX is the basis for timing analysis and performance verification, which are key to the success of an IC design. We address the trade-off between time cost and accuracy of PEX through machine learning techniques.
This innovative approach overcomes the limitations of the conventional TCAD-to-SPICE flow and contributes to effective design technology co-optimization (DTCO) to further advance semiconductor technologies.
