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    International Journals

    47. Hyunjoon Jeong, Jinyoung Choi, Hyungmin Cho, Sangmin Woo, Yohan Kim, Jeong-Taek Kong, and SoYoung Kim, "MOBO-Driven Advanced Sub-3-nm Device Optimization for Enhanced PDP Performance," in IEEE Transactions on Electron Devices, 2024, doi: 10.1109/TED.2024.3378224.

     

    46. H. Khac Le and SoYoung Kim, "Length-Dependent Deep Neural Network Based Modeling for High-Speed Channels," in IEEE Access, vol. 12, pp. 7624-7636, 2024, doi: 10.1109/ACCESS.2024.3351843.

     

    45. Jinyoung Choi, Hyunjoon Jeong, Sangmin Woo, Hyungmin Cho, Yohan Kim, Jeong-Taek Kong, and SoYoung Kim, "Enhancement and Expansion of the Neural network-Based Compact Model Using a Binning Method," vol. 12, pp. 65-73, 2024, in IEEE Journal of the Electron Devices Society, doi: 10.1109/JEDS.2023.3346380.

     

    44. Yohan Kim and SoYoung Kim, "Simulation Acceleration of Bit Error Rate Prediction and Yield Optimization of 3D V-NAND Flash Memory"in IEEE Access, vol. 11, pp.93956-93967, 2023, doi: 10.1109/ACCESS.2023.3309649.

     

    43. JunHa Suk, Yohan Kim, Jungho Do, GaRoom Kim, SangHoon Baek, JongWook Kye and SoYoung Kim, "Analytical Parasitic Resistance and Capacitance Models for Nanosheet Field-Effect Transistors," in IEEE Transactions on Electron Devices, vol. 70, no. 6, pp. 2941-2946, Jun. 2023, doi: 10.1109/TED.2023.3270398.

     

    42. Yohan Kim and SoYoung Kim, "A Process-Aware Compact Model for GIDL-Assisted Erase Optimization of 3-D V-NAND Flash Memory," in IEEE Transactions on Electron Devices, vol.70, no. 4, pp. 1664-1670, Apr. 2023, doi: 10.1109/TED.2023.3246024.

     

    41. Hyunjoon Jeong, Sangmin Woo, Jinyoung Choi, Hyungmin Cho, Yohan Kim, Jeong-Taek Kong, and SoYoung Kim, "Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors," in IEEE Journal of the Electron Devices Society, Vol. 11, pp. 153-160, 2023, doi: 10.1109/JEDS.2023.3246477.

     

    40. GiWon Kim and SoYoung Kim, "Design of Packaged Multi-radius Multi-path Solenoidal Inductor for Redistribution Layers"Journal of Semiconductor Technology and Science, vol.22, no.6, Dec.2022, doi: 10.5573/JSTS.2022.22.6.395.

     

    39. SangMin Woo, HyunJoon Jeong, JinYoung Choi, HyungMin Cho, Jeong-Taek Kong and SoYoung Kim, "Machine-Learning-Based Compact Modeling for sub-3-nm-Node Emerging Transistor", Electronics, MDPI Electronics, Electronics 2022, 11(17), 2761, Sep.2022, doi: 10.3390/electronics11172761.

     

    38. Songkil Yoo and SoYoung Kim, "Leakage Optimization of the Buried Oxide Substrate of Nanosheet Field-Effect Transistors", IEEE Transactions on Electron Devices, vol.69, no. 8, pp.4109-4114, Aug.2022, doi: 10.1109/TED.2022.3182300.

     

    37. TaeWoong Kim and SoYoung Kim, "Electronic design automation requirements for R2R printing foundry", Flexible and Printed Electronics, vol.7, no.1, Feb.2022, doi: 10.1088.2058-8585/ac4d3d.

     

    36. JunHa Suk, ChanYeop Ahn, S M Mojahidul Ahsan and SoYoung Kim,"A stable 4-bit ALU design for printed devices" Flexible and Printed Electronics, vol.7, no.1, Jan.2022, doi: 10.1088/2058-8585/ac49da.

     

    35. TaeWoong Kim, YoungBong Han, Hung Khac Le, JongWan Shim, KwangMo Yang, BumHee Bae, and SoYoung Kim, "Periodic Ground Structure for C-PHY Signaling in Mobile Application", Journal of Semiconductor Technology and Science, vol.21, no.5, Oct.2021, doi: 10.5573/JSTS.2021.21.5.311.

     

    34. Hung Khac Le, Hoang Van Nguyen, Youngbong Han, and SoYoung Kim,"Built-in Ring Transmission Line Structure for Signal Integrity Optimization of PAM4 Signaling in PCBs", IEEE Transactions on Electromagnetic compatibility, June 2021, doi: 10.1109/TEMC.2021.3078438.

     

    33. Hung Khac Le, and SoYoung Kim, "Machine Learning Based Energy-Efficient Design Approach for Interconnects in Circuits and Systems", Applied Sciences, MDPI. 2021, 11(3), 915, doi: 10.3390/app11030915.

     

    32. Saehoon Joung, and SoYoung Kim, "Core Insulator Nano Sheet Transistor and Structure Optimization to Improve Gate Electrostatic Characteristics", Journal of Nanoscience and Nanotechnology, vol. 20, no. 8, 2020, doi: 10.1166/jnn.2020.17800.

     

    31. Young Sik Lee, SoYoung Kim, and Tae-Hee Han, "Aging-Resilient Topology Synthesis of Heterogeneous Manycore Network-On-Chip Using Genetic Algorithm with Flexible Number of Routers," MDPI Electronics, Electronics 2019, 8, 1458; doi:10.3390/electronics8121458.

     

    30. Youngbong Han, SeoungHyuk Lee, and SoYoung Kim, "Radio Frequency Interference Analysis of Camera Modules and Antennas in Smartphones," IEIE Transactions on Smart Processing and Computing, pp.298-306, vol.8, no.4, August 2019, doi: 10.23919/ELINFOCOM.2019.8706353.

     

    29. Van Ha Nguyen, Hai Au Huynh, SoYoung Kim, Hanjung Song, “Active EMI reduction using Chaotic Modulation in Buck Converter with Relaxed Output LC FilterMDPI Electronics, vol. 7, no. 10, 2018, doi: 10.3390/electronics7100254.

     

    28. Youngbong Han, Hai Au Huynh and SoYoung Kim, “Pinwheel Meander-Perforated Plane Structure for Mitigating Power/Ground Noise in System-in-Package,” IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 562-569, vol. 8, no. 4,  April 2018, doi: 10.1109/TCPMT.2018.2798580.

     

    27. Hai Au Huynh, Youngbong Han, Sanghyeok Park, Jisoo Hwang, Eunseok Song and SoYoung Kim, “Design and Analysis of the DC-DC Converter With a Frequency Hopping Technique for EMI Reduction,” IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 546-553, vol. 8, no. 4,  April 2018, doi: 10.1109/TCPMT.2017.2788048.

     

    26. Soyeon Joo and SoYoung Kim, “Output-capacitor-free LDO design methodologies for high EMI immunity,” IEEE Transactions on Electromagnetic Compatibility, pp. 497-506, vol. 60, no. 2,  April 2018, doi: 10.1109/TEMC.2017.2727047.

     

    25. Soyeon Joo and SoYoung Kim, “PSR enhancement techniques for output-capacitor-free LDO regulator design,” Analog Integrated Circcuits and Signal Processing, vol. 93, no. 2, pp. 319-327, Oct. 2017, doi: 10.1007/s10470-017-1045-9.

     

    24. Soyeon Joo, Jintae Kim, and SoYoung Kim, "Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs," IEICE Transactions on Electronics Vol. E100-C, No. 5, pp. 504-512, May 2017, doi: 10.1587/transeke.E100.C.504.

     

    23. JungHun Kim, Hai Au Huynh, and SoYoung Kim, "Modeling of FinFET Parasitic Source/Drain Resistance With Polygonal Epitaxy ," IEEE Transactions on Electron Devices, pp.2072-2079, VOL. 64, NO. 5, MAY 2017, doi: 10.1109/TED.2017.2685527.

     

    22. Hai Au Huynh, Jeong-Min Jo, Wansoo Nah, SoYoung Kim, "EMC Qualification Methodology for Semicustom Digital Integrated Circuit Design," IEEE Transactions on Electromagnetic Compatibility, pp. 1-13, vol. 53, no. 10,  Oct 2016, doi: 10.1109/TEMC.2016.2561978.

     

    21. Ikchan Jang, Yoonmyung Lee, SoYoung Kim, Jintae Kim, "Power-Performance Tradeoff Analysis of CML-based High-Speed Transmitter Designs using Circuit-Level Optimization," IEEE Transactions on Circuit and Systems - I, pp. 540-550, vol. 63, no. 4, April 2016, doi: 10.1109/TCSI.2016.2528481.

     

    20. JinHyuk Jeong, Ho Lee, DongHae Kang, and SoYoung Kim, "Gate Engineering to Improve Effective Resistance of 28-nm High-k Metal Gate CMOS Devices," IEEE Transactions on Electron Devices, pp.259-264, vol.63, no.1, Jan. 2016, doi: 10.1109/TED.2015.2496502.

     

    19. KyungSoo Kim and SoYoung Kim," Design of Schmitt Trigger Logic Gates Using DTMOS for Enhanced Electromagnetic Immunity of Subthreshold Circuits," IEEE Transactions on Electromagnetic Compatibility, pp.963-972, vol. 57, no. 5, Oct. 2015, doi: 10.1109/TEMC.2015.2427992.

     

    18. Bo Pu, Kwang Ho Kim, SoYoung Kim and Wansoo Nah, "Modeling and Parameter Extraction  of Coplanar Symmetrical Meander Lines," IEEE Transactions on Electromagnetic Compatibility, pp. 375-383, vol. 57, no.3, June 2015, doi: 10.1109/TEMC.2014.2383383. 

     

    17. Hee Kwon Lee, Soojung Ryu, Seungbae Lee, SoYoung Kim and Wansoo Nah, "Electromagnetic Field Interference on Transmission Lines due to On-board Antenna,"  International Journal of Antennas and Propagation, vol. 2015, Article ID 104506, 12 pages, 2015, doi: 10.1155/2015/104506.

     

    16. Hai Au Huynh, Hak-Tae Lee, Wansoo Nah, and SoYoung Kim, "Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods," International Journal of Antennas and Propagation, vol. 2015, Article ID 497647, 11 pages, 2015, doi:10.1155/2015/497647.

     

    15. Ikchan Jang, Jintae Kim and SoYoung Kim, " Accurate delay models of CMOS CML circuits for design optimization," Analog Integrated Circuits and Signal Processing, pp. 297-307, vol.82, no.2, 2015, doi: 10.1007/s10470-014-0460-4.

     

    14. TaeYoon An, KyeongKeun Choe, Kee-Won Kwon, and SoYoung Kim, "Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance," Journal of Semiconductor Technology and Science, pp.525-536, vol.14, no.5, Oct. 2014, doi: 10.5573/JSTS.2014.14.5.525.

     

    13. NamKyoung Kim, Jisoo Hwang and SoYoung Kim, "EMI Prediction of Slew-Rate Controlled I/O Buffers by Full-Wave and Circuit Co-Simulation" Journal of Semiconductor Technology and Science, pp. 471-477, vol.14, no.4, August, 2014 , doi: 10.5573/JSTS.2014.14.4.471.

     

    12. NaHyun Kim, Wansoo Nah, SoYoung Kim, “Immunity Test for Semiconductor Integrated Circuits Considering Power Transfer Efficiency of the Bulk Current Injection Method,” Journal of Semiconductor Technology and Science, pp. 202-211, vol.14, no.2, Apr, 2014, doi: 10.5573/JSTS.2014.14.2.202.

     

    11. Jongmin Kim, Duc Long Luong, Wansoo Nah, SoYoung Kim, “Measurement of Multi-Port S-Parameters using Four-Port Network Analyzer,” Journal of Semiconductor Technology and Science, pp. 589-593, vol.13, no.6, Dec., 2013, doi: 10.5573/JSTS.2013.13.6.589.

     

    10. Bob Pu, Taeho Kim,  Jong-hyeon Kim,  SoYoung Kim, and Wansoo Nah, "Estimation of Transferred Power from a Noise Source to an IC with Forwarded Power Characteristics," Journal of Electromagnetic Engineering and Science, vol. 13, no. 4, pp233-239, Dec. 2013, doi: 10.5515/JKIEES.2013.13.4.233.

     

    9. Jeongha Park, Oh, S., SoYoung Kim, Wong, H.P., Wong S. S. “Impact of III–V and Ge Devices on Circuit Performance,”  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1189 – 1200, vol 21, issue 7, July, 2013, doi: 10.1109/TVLSI.2012.2210450.

     

    8. KwangWon Lee, TaeYoon An, SoYeon Joo, Kee-Won Kwon, and SoYoung Kim, “Modeling of Parasitic Fringing Capacitancein Multifin Trigate FinFETs,” IEEE Transactions on Electron Devices, pp. 1786 - 1789, vol. 60, no. 5, May, 2013, doi: 10.1109/TED.2013.2252467.

     

    7. SangKeun Kwak, Wansoo Nah and SoYoung Kim, “Electromagnetic Susceptibility Analysis of I/O Buffers Using the Bulk Current Injection Method,” Journal of Semiconductor Technology and Science, pp. 114-126, vol.13, no.2, Apr, 2013, doi: 10.5573/JSTS.2013.13.2.114.

     

    6. Hongjin Kim, SoYoung Kim and Kang-Yoon Lee, " A Low Power, Small Area Cyclic Time-to-Digital Converter in All-Digital PLL for DVB-SS Application," Journal of Semiconductor Technology and Science, pp. 114-126, vol.13, no.2, Apr, 2013, doi: 10.5573/JSTS.2013.13.2.145.

     

    5. Hak-Tae Lee, Larry A. Meyn and SoYoung Kim,  "Probabilistic Safety Assessment of Unmanned Aerial System Operations", Journal of Guidance, Control, and Dynamics, pp. 610-617, vol. 36, no. 2, Mar, 2013, doi: 10.2514/1.57572.

     

    4. HyungGu Park, SoYoung Kim and Kang-Yoon Lee, "A low-cost, wide-band DCO with an on-chip 3-D solenoid inductor in 0.13 μm digital CMOS," Analog Integrated Circuits and Signal Processing, pp. 507-515, vol.74, no.3, 2013, doi: 10.1007/s10470-012-0024-4.

     

    3. Hongjin Kim, SoYoung Kim and Kang-Yoon Lee, "Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application," Analog Integrated Circuits and Signal Processing, pp. 599-612, vol.74, no.3, 2013, doi: 10.1007/s10470-012-0020-8.

     

    2. SangKeun Kwak, YoungSic Jo, JeongMin Jo, and SoYoung Kim, “Power Integrity and Shielding Effectiveness Modeling of Grid Structured Interconnects on PCBs ,” Journal of Semiconductor Technology and Science, pp. 320-330, vol. 12, no.3, Sep, 2012, doi: 10.5573/JSTS.2012.12.3.320.

     

    1. Singh, R.,Jong-Kwan Woo, Hyunjoong Lee, So Young Kim, Suhwan Kim, “Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 749-762, vol. 59,  issue 4, Apr, 2012, doi: 10.1109/TCSI.2011.2169889.